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Private cache vs Shared Cache
Nanometer Naming Convention is Not a Physical Dimension
Analyzing Electron E1 Promises
IMEC's Updated Roadmap to 2039
IBM Z Mainframes
Where is the L3? It's virtual!
Introduction to IMEC and their Role
Main Lithography Machine Technology (EUV)
Embedded Market Power Constraints
IBM z15
IBM z16, Telum
Where is the L4? It's virtual!
Benefits for Gaming, for Intel
There's Plenty Moore Room: IBM's New 2nm CPU
Latency vs Capacity redux
Intel: We're Replacing PCBs with Glass Core
How E1 Tiles & Data Flow
Polishing a wafer
Fujitsu’s New ARM Chip: Focused, Fast, and Unlike Anything Else
Your Next CPU is Bigger Than Your HEAD 🤯 Cerebras Wafer Scale 2
Redefining Large Silicon
The world of AI Processors
Why are Processors Square (and Wafers Circular)?
Wafer Size
Salami
Photolithography
Is this the end of SSDs?!? Samsung's new 512 GB DDR5-7200
Arm vs Qualcomm: I'm in the Lawsuit! 🤯
4,000,000,000,000 Transistors, One Giant Chip (Cerebras WSE-3)
NA and EUV
Backside Power Delivery Innovation
Nanosheet Era (N2 to A10) and Fork Sheet Transistors
2D Materials (Millennium Disulfide, Tungsten DiTelluride)
Complimentary FETs (CFETs) and Double Density
General Purpose, New Execution Model
Software and Compiler Toolchain
Performance Claims and Benchmarks
Intel's Newest $350 Million Machine
Update to Intel's AI Silicon
NVIDIA's Latest Memory Technology: A Breakthrough?
Ian Interviews #12: Pat Gelsinger, Intel CEO (Q&A Roundtable)
Tesla Dojo AI Supercomputer Deep Dive and Analysis
Where $17 billion has gone in AI
Path Tracing Done Right? A Deep Dive into Bolt Graphics
The True Cost of Processor Manufacturing: TSMC 7nm
Time and Cost
How To Get More USB Ports Using ZERO Desk Space
Intro
Square and Circle, Bless the Wafer!
How to make a wafer
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